The present invention relates generally to memory devices and in particular the present invention relates to drivers for memory circuits.
Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicate a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write.
Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. The transistors can be erased to restore the threshold voltage of the transistor. The memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. These non-volatile memory devices are commonly referred to as flash memories.
The non-volatile memory cells are fabricated as floating gate memory cells and include a source region and a drain region that is laterally spaced apart from the source region to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and can also made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is xe2x80x9cfloatingxe2x80x9d in dielectric so that it is insulated from both the channel and the control gate.
In high performance flash memories, such as synchronous flash memories, large loads are selected in the memory array during a read or write cycle. These loads must be selected in a very short time. Further, as components continue to shrink, and as operating power continues to decrease, components that consume less power are also needed. In high performance memories, on each bitline of a memory array, there are gates for access transistors. In modern memories, there are on the order of 4000 bitlines. Each bitline has a pass transistor between a global bitline and the local bitline that is turned on for memory access in an active cycle of the memory. Turning on 4000 transistors creates a large capacitance that is turned on and off during each shift from bank to bank of a memory array during a read cycle of the memory. Typically, this row activation occurs every 20 nanoseconds. This can consume on the order of 10 or more milliamps of current.
A pumped voltage circuit supplies a voltage Vpx for the gates of the pass transistors. This pumped voltage uses a supply voltage for the memory as its source. As supply voltages continue to drop, presently to on the order of 1.6 to 1.8 volts, pumping Vpx to about 5 volts becomes increasingly less power efficient, especially if there is a current drain due to the large capacitance of 4000 bitline transistors, since Vpx is a pumped voltage and not a supply voltage. This pumped voltage is quickly drained of an unacceptable amount of current if it is used to supply the current required for loading 4000 bitlines. To supply 10 milliamps from the pumped voltage circuit requires on the order of 30 milliamps from Vcc, which yields very low power efficiencies. The current that gets used for Vpx is very expensive.
The gates on the pass transistors need to be pulled up to Vcc quickly to allow gate selection and activation within the very short time periods used in flash memories. Once a potential at or near Vcc is present at the gates, they need to be raised to a voltage slightly above Vcc, but time is not as critical for the final increase.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a driver that does not tax the current of a pumped gate voltage supply.
The above-mentioned problems with gate selection and power consumption in flash memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a driver for a memory array includes an enable circuit providing an enable signal, a pull down transistor having its gate connected to the enable signal to ground an output node when the enable signal is disabled, and a pass transistor having its gate connected through a first p-type pull-up transistor connected between a pumped voltage and the gate of the pass transistor. An inverter is connected between the enable circuit output and the pass transistor, and a second pull down transistor is connected between ground and the gate of the pass transistor. Two inverters are coupled in series between the output of the first inverter and the gate of the second pull down transistor. A second p-type transistor is connected between the pumped voltage and the output node, the gate of the second p-type transistor connected to the gate of the pass transistor.
In another embodiment, a driver for a memory array pass transistor block includes a first path for providing a supply voltage to an output node upon initiation of a read cycle, and a second path for providing a pumped voltage to the output node after the output node receives the supply voltage, where the pumped voltage is greater than the supply voltage.
In yet another embodiment, a memory device includes an array of memory cells, control circuitry to read, write and erase the memory cells, and a driver circuit to control read access. The driver circuit includes a first path for providing a supply voltage to the output upon initiation of a read cycle, and a second path for providing a pumped voltage above the supply voltage after providing the supply voltage.
In still another embodiment, a flash memory device includes an array of floating gate memory cells, control circuitry to read, write and erase the floating gate memory cells, and a driver circuit to control read access. The driver circuit includes a NAND gate providing a read signal, a pull down transistor having its gate connected to the read signal, to ground an output node when the read signal is disabled, a pass transistor having its gate connected through a first p-type pull-up transistor connected between a pumped voltage and the gate of the pass transistor, an inverter connected between the NAND gate output and the pass transistor, a second pull down transistor connected between ground and the gate of the pass transistor, a series connection of two inverters connected between the output of the first inverter and the gate of the second pull down transistor, and a second p-type transistor connected between the pumped voltage and the output node, the gate of the second p-type transistor connected to the gate of the pass transistor.
In yet another embodiment, a method of operating a circuit includes holding an output node at a low potential, and maintaining a pass transistor ready to supply the output node with a high potential during a read cycle. A supply voltage is passed to the output node without using a pumped voltage upon initiation of the read cycle, and a pumped voltage is passed to the output node to elevate the output node voltage above the supply voltage once the output node reaches the supply voltage.
In still yet another embodiment, a method of operating a read cycle in a memory includes supplying an output voltage to the gates of an array of pass transistors of a memory array, the output voltage ramped to a supply voltage without using a pumped voltage, and raised above a supply voltage with a pumped voltage.
In another embodiment, a method of providing a gate voltage for pass transistors of a memory array includes providing a supply voltage substantially immediately upon initiation of a read cycle, and delaying supplying a pumped voltage to raise the gate voltage above the supply voltage until the gate voltage has reached the supply voltage.
Other embodiments are described and claimed.